Interconnect delay minimization through interlayer via placement in 3-D ICs

The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via location, with fixed vertical length, the optimum vertical through via location that minimizes the propagation delay of an interconnect line connecting two circuits on different planes is determined. The optimum vertical through via location and length or, equivalently, the number of physical planes traversed by the vertical through via, are determined for varying the placement of the connected circuits. Design expressions for the optimal via locations and lengths have been developed to support placement and routing algorithms for 3-D ICs. Categories and Subject Descriptors B.7.2 [Design Aids] General Terms: Performance, Design.

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Vasilis F. Pavlidis, Eby G. Friedman
• Keywords: GLVLSI 2005, Interconnect, Propagation Delay, Vertical Length, VLSI