Library-less synthesis for static CMOS combinational logic circuits

Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield a good synthesis results over many blocks or even for an entire chip. Consequently, this approach precludes an optimal design of individual blocks which may need custom structures. In this paper we present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. Our technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of our resynthesized circuits.

• Type: Conference
• Year: 1997
• Where: ICCAD
• Authors: Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw
• Keywords: CMOS Circuits, Hardware, ICCAD 1997, Library Mapping Phase, Techniques Optimize Cmos