A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make `new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Kris Tiri, Ingrid Verbauwhede
• Keywords: DATE 2004, DPA Resistant Crypto, Hardware, Power Consumption, Standard Cells