Sciweavers

DATE
2004
IEEE
149views Hardware» more  DATE 2004»
14 years 2 months ago
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
Kris Tiri, Ingrid Verbauwhede
ISQED
2006
IEEE
124views Hardware» more  ISQED 2006»
14 years 5 months ago
DFM Metrics for Standard Cells
Design for Manufacturability (DFM) is becoming increasingly important as process geometries shrink. Conventional design rule pass/fail is not adequate to quantify DFM compliance. ...
Robert C. Aitken
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
14 years 5 months ago
A Generic Standard Cell Design Methodology for Differential Circuit Styles
In this paper we present a generic methodology for the rapid generation and implementation of standard cell libraries for differential circuit design styles. We demonstrate a syst...
Stéphane Badel, Erdem Guleyupoglu, Ozgur In...
ISPD
2010
ACM
205views Hardware» more  ISPD 2010»
14 years 5 months ago
Total sensitivity based dfm optimization of standard library cells
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
Yongchan Ban, Savithri Sundareswaran, David Z. Pan