Low-Energy DSP Code Generation Using a Genetic Algorithm

This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm based code generator (GCG), and an instruction-level power model for this processor. Our code generator is capable of reducing the power dissipation of target applications by means of two techniques: First, GCG minimizes the number of memory accesses by using a special list-scheduling algorithm. This technique makes it possible to perform graph based code selection and to take into account the high interdependencies of the subtasks of code generation by phase coupling. In addition, GCG optimizes the scheduling of processor instructionswith respect to the instruction-level power model based on a gate level simulation. Experimental results for several benchmarks show the effectiveness of our approach1 .

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis
• Keywords: Algorithm Based Code, Graph Based Code, Hardware, ICCD 2001, Low-energy Code Generation