A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagating test responses from the core outputs. In this paper, we present a design for testabilityand symbolic test generation technique for testing such core-based systems on a chip. The proposed method consists of two parts: (i) core-level design for testability to make each core testable and transparent, the latter needed to propagate test data through the cores, and (ii) system-level design for testability and test generation to ensure the justification and propagation of the precomputed test sequences and test responses of the core. Since the hierarchical testability analysis technique used t...

• Type: Conference
• Year: 1997
• Where: ITC
• Authors: Indradeep Ghosh, Niraj K. Jha, Sujit Dey
• Keywords: Hardware, ITC 1997, Test Generation, Test Responses, Test Sequences