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ITC
1997
IEEE
119views Hardware» more  ITC 1997»
14 years 4 months ago
Testability Analysis and ATPG on Behavioral RT-Level VHDL
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
ITC
1997
IEEE
107views Hardware» more  ITC 1997»
14 years 4 months ago
On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
Benoît R. Veillette, Gordon W. Roberts
ITC
1997
IEEE
92views Hardware» more  ITC 1997»
14 years 4 months ago
Capacitive Leadframe Testing
Capacitive Leadframe testing is an effective approach for detecting faults in printed circuit boards. Capacitance measurements, however, are affected by mechanical variations duri...
Ted T. Turner
ITC
1997
IEEE
92views Hardware» more  ITC 1997»
14 years 4 months ago
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper...
Raghuram S. Tupuri, Jacob A. Abraham
ITC
1997
IEEE
121views Hardware» more  ITC 1997»
14 years 4 months ago
BIST-Based Diagnostics of FPGA Logic Blocks
: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance....
Charles E. Stroud, Eric Lee, Miron Abramovici
ITC
1997
IEEE
93views Hardware» more  ITC 1997»
14 years 4 months ago
Fault Diagnosis in Scan-Based BIST
A deterministic-partitioning technique and an improved analysis scheme for fault diagnosis in Scan-Based BIST is proposed. The incorporation of the superposition principle to the ...
Janusz Rajski, Jerzy Tyszer
ITC
1997
IEEE
123views Hardware» more  ITC 1997»
14 years 4 months ago
Modifying User-Defined Logic for Test Access to Embedded Cores
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...
Bahram Pouya, Nur A. Touba
ITC
1997
IEEE
94views Hardware» more  ITC 1997»
14 years 4 months ago
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data
Transient Signal Analysis is a digital device testing method that is based on the analysis of voltage transients at multiple test points and on IDD switching transients on the sup...
James F. Plusquellic, Donald M. Chiarulli, Steven ...
ITC
1997
IEEE
90views Hardware» more  ITC 1997»
14 years 4 months ago
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Pe...
ITC
1997
IEEE
75views Hardware» more  ITC 1997»
14 years 4 months ago
An Efficient Scheme to Diagnose Scan Chains
Sridhar Narayanan, Ashutosh Das