Low-power design of sequential circuits using a quasi-synchronous derived clock

– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master clock and using it to isolate the flip flops in the circuit from the unwanted triggering action of the master clock. An example design of a decimal counter demonstrates the large power saving and improved performance of the resulting circuit.

• Type: Conference
• Year: 2000
• Where: ASPDAC
• Authors: Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu
• Keywords: ASPDAC 2000, Circuit Design Technique, Hardware, Master Clock, Quasi-synchronous Derived Clock