circuit design technique

ASPDAC
2000
ACM

83views Hardware» more ASPDAC 2000»

Low-power design of sequential circuits using a quasi-synchronous derived clock

14 years 3 months ago

– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...

Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu

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DAC
2007
ACM

131views Computer Architecture» more DAC 2007»

Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop

15 years 15 days ago

Download cobweb.ecn.purdue.edu

This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...

Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy

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