A low power FPGA routing architecture

— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important criterion that needs improvement. In this paper, we propose an interconnect architecture, where voltage scaling is applied within the programmable interconnect structure of the FPGA. We present an evaluation of the overhead associated with dual-Vdd-dual-Vt interconnect architecture and present results on the impact of this routing architecture on area and delay. Our experiments reveal that an average reduction of 23.45 % (as high as 47 %) in total

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Somsubhra Mondal, Seda Ogrenci Memik
• Keywords: Dual-Vdd-dual-Vt Interconnect Architecture, Interconnect Architecture, ISCAS 2005, Programmable Interconnect Structure