Vdd programmability to reduce FPGA interconnect power

Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect fabric to reduce FPGA interconnect power. There are three Vdd states for interconnect switches: high Vdd, low Vdd and power-gating. We develop a simple design flow to apply high Vdd to critical paths and low Vdd to non-critical paths and to power gate unused interconnect switches. We carry out a highly quantitative study by placing and routing benchmark circuits in 100nm technology to illustrate the power saving. Compared to single-Vdd FPGAs with optimized but non-programmable Vdd level for the same target clock frequency, our new FPGA fabric on average reduces interconnect power by 56.51% and total FPGA power by 50.55%. Due to the highly low utilization rate of routing switches, majority of the power reduction is achieved by power gating unused routing buffers. In contrast, recent work that considers Vdd p...

• Type: Conference
• Year: 2004
• Where: ICCAD
• Authors: Fei Li, Yan Lin, Lei He
• Keywords: FPGA Interconnect Power, Hardware, ICCAD 2004, Reduces Interconnect Power, Total Fpga Power