Low-Power High-Speed 180-nm CMOS Clock Drivers

- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were fabricated using 0.18- m CMOS technology. The first and second stages of the driver consisted of a single inverter and m inverters, respectively, and the register array stage was constructed with N delay flip-flops (D-FFs). A single inverter in the second stage drove N/m D-FFs where N was fixed at 40 and m varied from 1 to 40. Minimum PT and tdT were 251 W and 0.640 ns, respectively and were both obtained at an m of 8. These values were 48.6% and 29.4% of maximum PT and tdT, respectively. Simulated and measured results agreed well with these SPICE simulated results.

• Type: Conference
• Year: 2007
• Where: ASPDAC
• Authors: Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi
• Keywords: ASPDAC 2007, Clock Drivers, Hardware, Register Array, Single Inverter