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16
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ASPDAC
2007
ACM
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ASPDAC 2007
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Low-Power High-Speed 180-nm CMOS Clock Drivers
14 years 16 days ago
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www.cecs.uci.edu
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobaya...
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