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    ASPDAC
    2007
    ACM
    82views Hardware» more  ASPDAC 2007»
    Low-Power High-Speed 180-nm CMOS Clock Drivers
    14 years 4 months ago
    Low-Power High-Speed 180-nm CMOS Clock Drivers
    Download  www.cecs.uci.edu
    - The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
    Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobaya...
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