Low-power process-variation tolerant arithmetic units using input-based elastic clocking

In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of

• Type: Conference
• Year: 2007
• Where: ISLPED
• Authors: Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy
• Keywords: Arithmetic Units, Hardware, ISLPED 2007, Possible Delay Failures, Variations And/or Voltage