A low-power switched-current algorithmic A/D converter

This paper reports the development of a low-power switchedcurrent algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter uses modified S2 I type current copiers to reduce the overall area and power consumption. The analog portion of the converter occupies only 0.35mm2 area in 3

• Type: Conference
• Year: 1999
• Where: ISCAS
• Authors: A. Tezel, T. Akin
• Keywords: Algorithmic A/d Converter, Bit Conversion, Hardware, ISCAS 1999, Power Consumption