Low Transition LFSR for BIST-Based Applications

Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within random test pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns (fed to a combinational circuit) and consecutivebits (sent to a scan chain). LT-LFSR is independentof circuit under test and flexible to be used for both BIST and scan-based BIST architectures. The experimental results for ISCAS’85 and ’89 benchmarks, confirm up to 77% and 49% reduction in average and peak power, respectively.

• Type: Conference
• Year: 2005
• Where: ATS
• Authors: Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed
• Keywords: ATS 2005, Consecutive Patterns, Hardware, Test Pattern, Transition Test Pattern