Mapping Applications to an FPFA Tile

Abstract— This paper introduces a transformational design method which can be used to map code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Dataflow graph (CDFG), which is minimized using a set of behaviour preserving transformations such as dependency analysis, common subexpression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Michèl A. J. Rosien, Yuanqing Guo, Gerard J. M. Smit, Thijs Krol
• Keywords: Behaviour Preserving Transformations, Control Dataflow Graph, DATE 2003, Hardware, Minimized Graph