Marsh: min-area retiming with setup and hold constraints

This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock period c, our algorithm either outputs a retimed version of G satisfying setup and hold constraints or reports that such a solution is not possible, in OjV 3jlogjVjlogjVjC steps, where jVj corresponds to number of gates in the circuit and C is equal to the number of registers in the circuit. This is the first polynomial time algorithm ever reported for min-area retiming with constraints on both long and short-paths. An alternative problem formulation that takes practical issues in to consideration and lowers the problem complexity is also developed. Both the problem formulations have many parallels with the original formulation of long-path only retiming by Leiserson and Saxe and all the speed improvements that have been obtained on that technique are likely to be valid for improving the performance of the te...

• Type: Conference
• Year: 1999
• Where: ICCAD
• Authors: Vijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi
• Keywords: Hardware, ICCAD 1999, Min-area Retiming, Polynomial Time Algorithm, Problem Formulations