An efficient retiming algorithm under setup and hold constraints

In this paper we present a new efficient algorithm for retiming sequential circuits with edge-triggered registers under both setup and hold constraints. Compared with the previous work [17], which computed the minimum clock period in O(|V|3|E|lg|V|) time, our algorithm solves the same problem in O(|V|2|E|) time. Experimental results validate the efficiency of our algorithm. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circuits--Design Aids; J.6 [Computer-Aided Engineering]: Computer-Aided Design General Terms Algorithms, Performance, Design Keywords Retiming

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: Chuan Lin, Hai Zhou
• Keywords: Computer-aided Design, Computer-Aided Engineering, DAC 2006, Design Automation, Minimum Clock Period