Memory Arbitration and Cache Management in Stream-Based Systems

With the ongoing advancements in VLSI technology, the performance of an embedded system is determined to a large extend by the communication of data and instructions. This results in new methods for on- and off-chip communication and caching schemes. In this paper, we use an arbitration scheme that exploits the characteristics of continuous ’media’ streams while minimizing the latency for random (e.g. CPU) memory accesses to background memory. We also introduce a novel caching scheme for a streambased multiprocessor architecture, to limit as much as possible the amount of on-chip buffering required to guarantee the throughput of the continuous streams. With these two schemes we can build an architecture for media processing with optimal flexibility at run-time while performance guarantees can be determined at compile-time.

• Type: Conference
• Year: 2000
• Where: DATE
• Authors: Françoise Harmsze, Adwin H. Timmer, Jef L. van Meerbergen
• Keywords: DATE 2000, Hardware, Ongoing Advancements, Streambased Multiprocessor Architecture, VLSI Technology