Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays

This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to multiple memory arrays are often di cult to route, and are often part of the critical path of circuit implementations. The memory-to-memory connection structure proposed in this paper allows for the e cient implementation of these nets, resulting in a reduction in memory access time of up to 25 and a slight improvement in routability.

• Type: Conference
• Year: 1997
• Where: FPGA
• Authors: Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
• Keywords: Embedded Memory Arrays, FPGA, FPGA 1997, Memory Arrays, Multiple Memory Arrays