A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition

: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into subcircuits, and the upper bound is approximately computed as the sum of maximum switching gates for all subcircuits. In order to increase the accuracy, we adopted an evaluation function that takes account of both the interconnections among subcircuits and the number of generated subcircuits. Experimental results for ISCAS circuits show that the method efficiently evaluates the upper bounds of switching gates.

• Type: Conference
• Year: 1999
• Where: ASPDAC
• Authors: Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
• Keywords: ASPDAC 1999, Hardware, Simultaneous Switching Gates, Switching Gates, Upper Bounds