A Methodology for Generating Application Specific Tree Multipliers

Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have not been considered for automatic multiplier generation because they have been conszdered to be irregular. In this paper, a recursive methodology for generating n-2 compressors (for n in the range 3 5 n 5 64) using the basic cells 3-2 and 4-2 is presented. This methodology results in a highly regular and modular layout that can be automatically generated. The performance of the resulting compressors is competitive with detailed full-custom design. The area and latency of the resdting layout for any n is predictable to a faar degree of accnracy.

• Type: Conference
• Year: 1993
• Where: VLSID
• Authors: S. Ramanathan, Nibedita Mohanty, V. Visvanathan
• Keywords: Automatic Multiplier Generation, Specific Multipliers, Tree Multipliers, VLSI, VLSID 1993