Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures

— We discuss the design of CMOS MEMS in a 3D SOI-CMOS technology. We present layout architectures, preliminary mechanics modeling using finite element analysis and release process flows. An accelerometer structure is used as the model system with electronics embedded into a suspended proof mass. A prototype chip is fabricated in the MIT Lincoln Laboratories that includes test structures and systems for both a capacitive sensed and interferometric sensed accelerometers. I. 3D SOI-CMOS TECHNOLOGY The Massachusetts Institute of Technology Lincoln Laboratory(MITLL) 3D CMOS process opens design opportunities for unique microsystems structures in CMOS MEMS. One of the biggest drawbacks of CMOS MEMS is the wasted CMOS area necessary to fabricate the mechanical structure in the CMOS die. As we will show in this paper, with a 3D CMOS technology the amount of area wasted can be greatly reduced. The MITLL 3D process consists of three individually fabricated 0.18µm SOI CMOS wafers or tiers ve...

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Francisco Tejada, Andreas G. Andreou
• Keywords: CMOS, CMOS MEMS, ISCAS 2006, SOI CMOS Wafers