In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput f...
Sunghyun Park, Tushar Krishna, Chia-Hsin Owen Chen...
This paper reviews recent developments in vehicular radar at 60 GHz and above, with a focus on low cost integrated antennas. We investigate a number of radar and communication ante...
Felix Gutierrez Jr., Theodore S. Rappaport, James ...
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
A CMOS voltage reference, based on the difference between the gate-source voltages of two NMOS transistors, has been realized with AMS 0.35 m CMOS technology (Vthn=0.45 V and Vthn=...
End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in...
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
A new topology for translinear filters in CMOS IC technology is presented. This translinear filter is based on the exponential relation of passive PN-diodes in CMOS technology whi...