Sciweavers

DAC
2012
ACM
12 years 2 months ago
Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI
In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput f...
Sunghyun Park, Tushar Krishna, Chia-Hsin Owen Chen...
VTC
2010
IEEE
150views Communications» more  VTC 2010»
13 years 10 months ago
Millimeter-Wave CMOS Antennas and RFIC Parameter Extraction for Vehicular Applications
This paper reviews recent developments in vehicular radar at 60 GHz and above, with a focus on low cost integrated antennas. We investigate a number of radar and communication ante...
Felix Gutierrez Jr., Theodore S. Rappaport, James ...
TCAD
2010
106views more  TCAD 2010»
13 years 10 months ago
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimo...
MJ
2006
118views more  MJ 2006»
14 years 11 days ago
Ultra-low-power temperature compensated voltage reference generator
A CMOS voltage reference, based on the difference between the gate-source voltages of two NMOS transistors, has been realized with AMS 0.35 m CMOS technology (Vthn=0.45 V and Vthn=...
Giuseppe de Vita, Giuseppe Iannaccone
IEICET
2006
79views more  IEICET 2006»
14 years 13 days ago
System LSI: Challenges and Opportunities
End of CMOS scaling has been discussed in many places since the late 90's. Even if the end of CMOS scaling is irrelevant, it is for sure that we are facing a turning point in...
Tadahiro Kuroda
GLVLSI
2007
IEEE
173views VLSI» more  GLVLSI 2007»
14 years 18 days ago
Modeling and estimating leakage current in series-parallel CMOS networks
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...
Paulo F. Butzen, André Inácio Reis, ...
CODES
2008
IEEE
14 years 2 months ago
Design and defect tolerance beyond CMOS
It is well recognized that novel computational models, devices and technologies are needed in order to sustain the remarkable advancement of CMOS-based VLSI circuits and systems. ...
Xiaobo Sharon Hu, Alexander Khitun, Konstantin K. ...
ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
14 years 4 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
14 years 4 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev
ISCAS
2002
IEEE
97views Hardware» more  ISCAS 2002»
14 years 5 months ago
High-frequency dynamic translinear and log-domain circuits in CMOS technology
A new topology for translinear filters in CMOS IC technology is presented. This translinear filter is based on the exponential relation of passive PN-diodes in CMOS technology whi...
Sandro A. P. Haddad, Wouter A. Serdijn