Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

22

ASPDAC
2010
ACM

favoriteEmaildiscussreport

119views Hardware» more ASPDAC 2010»

Minimizing clock latency range in robust clock tree synthesis

13 years 8 months ago

Minimizing clock latency range in robust clock tree synthesis

Download www.asp-dac.itri.org.tw

Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen

Real-time Traffic

ASPDAC 2010 | Hardware |

claim paper

Related Content

» Clock tree synthesis with datapath sensitivity matching

» Novel binary linear programming for high performance clock mesh synthesis

» Clock buffer and wire sizing using sequential programming

» Exploring highspeed lowpower hybrid arithmetic units at scaled supply and adaptive clockst...

Post Info
More Details (n/a)

Added	28 Feb 2011
Updated	28 Feb 2011
Type	Journal
Year	2010
Where	ASPDAC
Authors	Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen

Comments (0)