This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enabl...
This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling ...
Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are ...
Heterogeneous multiprocessor system-on-chips (MPSoCs) which consist of cores with various power and performance characteristics can customize their configuration to achieve higher ...
This paper presents a 60 GHz direct-conversion transmitter in 65 nm CMOS technology. The power amplifier consists of 4-stage transistors. The circuit model of de-coupling capacitor...
Naoki Takayama, Kota Matsushita, Shogo Ito, Ning L...