Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program

In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrivaltimes, besides the gate delay, we reduce the number of the LP constraints to be linear in circuit size. For example, the 469-gate c880 circuit requires 3,611 constraints as comparedto the 6.95millionconstraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimizeall ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34% peak and 38% average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of th...

• Type: Conference
• Year: 2003
• Where: VLSID
• Authors: Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
• Keywords: Computer Architecture, Delay Bu Ers, Exact Lp Solution, Gate Delay, VLSID 2003