CMOS Circuit Design for Minimum Dynamic Power and Highest Speed

{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized by an inertial delay and separate delays between its inputs and output. The technology constraint, related to feasible ranges of lengths and widths of transistors, is speci ed by a parameter ub. It is the upper bound on the di erence between the input to output delays corresponding to any pair of inputs of a gate. We formulate a linear program (LP) whose size is proportional to the circuit size. This LP determines the inertial delay as well as input to output delays for each gate of the circuit with the given ub, such that all glitches are eliminated and the overall delay of the circuit is minimized. Because of the additional exibility in specifying gate delays, the glitch suppression is guaranteed without any delay bu ers. Hence this design consumes less power than those designed by other methods. We designed...

• Type: Conference
• Year: 2004
• Where: VLSID
• Authors: Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell
• Keywords: Computer Architecture, Delay Bu Ers, Inertial Delay, Overall Delay, VLSID 2004