Module Generation of Complex Macros for Logic-Emulation Applications

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design veri cation. Using an emulator, designers can realize designs through a software con guration process and perform real-time design veri cation before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shortening the Time-To-Emulation TTE is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logicemulation applications, which is able to generate macro cells of arbitrarily complex functions described in Highlevel Descriptive Languages HDLs. Furthermore, the module generator can e ectively generate a multipleFPGA macro for large macros which can not t in a single FPGA chip. Experiments using the module g...

• Type: Conference
• Year: 1997
• Where: FPGA
• Authors: Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
• Keywords: Design Processing Time, Design Veri Cation, FPGA, FPGA 1997, Module Generator