A More Effective CEFF

Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for drivers with lumped capacitive loads. This necessitates the translation of the actual loading and interconnect parasitics into a single effective capacitance [12]. Existing approaches to perform that translation are either iterative in nature or involve iterative procedure to solve nonclosed form equations and thus costly in CPU time. This paper presents a new accurate and simple closed form approach to deal with effective capacitance.

• Type: Conference
• Year: 2005
• Where: ISQED
• Authors: Sani R. Nassif, Zhuo Li
• Keywords: Effective Capacitance, Hardware, ISQED 2005, Lumped Capacitive Loads, Single Effective Capacitance