A multiple clocking scheme for low power RTL design

This paper presents an eective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed by n non-overalapping clocks. The idea is is to operate each module only during its corresponding duty cycle at a frequency f=n to reduce power. power. However, the overall eective frequency of the circuit remains f, the single clock frequency. The scheme uses a resource allocation algorithm to synthesize clock module partitions at the RTL. The allocation avoids combinational power consumption during the o duty cycles of each module. The method has been implemented on Sparcstation machines using a commercial CADtool which includes an activitybased power estimator. Experimental results and comparisons of the multiple clocking scheme to single clock (gated and ungated) designs are reported, entailing power savings up to 50%.

• Type: Conference
• Year: 1995
• Where: ISLPED
• Authors: Christos A. Papachristou, Mark Spining, Mehrdad Nourani
• Keywords: Hardware, ISLPED 1995, Multiple Clocking Scheme, Power Rtl Circuit, Single Clock