Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates

This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We present techniques to minimize EX-SOPs, which is an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. We conjecture that, when n is sufficiently large, an EX-SOP for n-bit adder requires at most 2n products while an ordinary sumof-products expression (SOP) requires 6 2n ;4n ;5 products. Experimental results for two- and four-valued benchmark functions show that the proposed method produces better EX-SOPs than existing methods.

• Type: Conference
• Year: 1999
• Where: ISMVL
• Authors: Debatosh Debnath, Tsutomu Sasao
• Keywords: Hardware, ISMVL 1999, Programmable Logic Arrays, Two-input Exor Gate, Two-valued Output Functions