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    ISMVL
    1999
    IEEE
    76views Hardware» more  ISMVL 1999»
    Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
    14 years 8 months ago
    Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
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    This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
    Debatosh Debnath, Tsutomu Sasao
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