A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects by postponing the UpdateDR with EXTEST instruction. Furthermore 2log(N+2) interconnect test patterns are proposed for both static and delay testing.

• Type: Conference
• Year: 2000
• Where: DATE
• Authors: Sungju Park, Taehyung Kim
• Keywords: Boundary Scan Design, DATE 2000, Hardware, Interconnect Test Patterns, Test Delay