Noise-tolerant dynamic circuit design

-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energyefficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino

• Type: Conference
• Year: 1999
• Where: ISCAS
• Authors: Lei Wang, Naresh R. Shanbhag
• Keywords: Deep Submicron, Deep Submicron Technology, Dynamic Circuit Technique, Hardware, ISCAS 1999