Non-gaussian statistical interconnect timing analysis

This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performing timing analysis of RLC networks with step inputs, under both Gaussian and non-Gaussian sources of variation, is presented. In this framework, resistance, inductance, and capacitance of the RLC line are modeled in a canonical first order form and used to produce the corresponding propagation delay and slew (time) in the canonical first-order form. To accomplish this step, mean, variance, and skewness of delay and slew distributions are obtained in an efficient, yet accurate, manner. The proposed framework can be extended to consider higher order terms of the various sources of variation. Experimental results show average errors of less than 2% for the mean, variance and skewness of interconnect delay and slew while achieving orders of magnitude speedup with respect to a Monte Carlo simulation with 104 sample...

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
• Keywords: DATE 2006, Hardware, Interconnect Timing Analysis, Statistical Static Timing Analysis, Timing Analysis