Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits

Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have proposed a new algorithm to realize dual threshold CMOS circuits. Our algorithm produces significantly better results for the ISCAS benchmark circuits compared to the reported results.

• Type: Conference
• Year: 2001
• Where: VLSID
• Authors: Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal
• Keywords: Computer Architecture, Dual Threshold CMOS, ISCAS Benchmark Circuits, Low Threshold Voltage, VLSID 2001