On optimal physical synthesis of sleep transistors

Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: the min-area sleep transistor insertion (and sizing) (TIS) problem with respect to a fixed P/G network, and the simultaneous sleep transistor insertion and P/G network sizing (TIPGS) problem to minimize the weighted area of sleep transistors and P/G network. We show that there may exist multiple sleep transistor insertion solutions that all lead to a same minimum area in the TIS and TIPGS problems. We develop optimal algorithms to TIS and TIPGS problems by modeling the circuit as a single current source, and then extend to the case modeling the circuit as distributed current sources. Compared with the best known approach, our algorithms achieve area reduction by up to

• Type: Conference
• Year: 2004
• Where: ISPD
• Authors: Changbo Long, Jinjun Xiong, Lei He
• Keywords: Hardware, ISPD 2004, P/G Network, Sleep Transistor, Sleep Transistor Insertion