JCP
2008
13 years 11 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
DAC
1997
ACM
14 years 3 months ago
1997
ACM
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
ISPD
2004
ACM
14 years 4 months ago
2004
ACM
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
DATE
2008
IEEE
14 years 5 months ago
2008
IEEE
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
ISQED
2010
IEEE
14 years 6 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...