Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performance/area characteristics of large caches, such as wire models (width/spacing/repeaters), signaling strategy (RC/differential/transmission), router design, etc. Yet, to date, there exists no analytical tool that takes all of these parameters into account to carry out a design space exploration for large caches and estimate an optimal organization. In this work, we implement two major extensions to the CACTI cache modeling tool that focus on interconnect design for a large cache. First, we add the ability to model different types of wires, such as RC-based wires with different power/delay characteristics and differential low-swing buses. Second, we add the ability to model Non-uniform Cache A...

• Type: Conference
• Year: 2007
• Where: MICRO
• Authors: Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
• Keywords: Design Space Exploration, Hardware, Interconnect Design, Large Cache, MICRO 2007