Is overlay error more important than interconnect variations in double patterning?

Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interconnect layer. Consequently, mask shift-induced overlay errors introduce additional variability into interconnect coupling capacitances. An important open question is whether overlay-induced performance impacts are more significant than performance variations caused by variability in interconnects. We provide TCAD as well as chip-level analyses to determine whether overlay error should receive more attention than interconnect variations during interconnect manufacturing. We develop conclusions to help determine which component should be given more importance in specific double patterning process variants. Categories and Subject Descriptors B.7.2 [INTEGRATED CIRCUITS]: Design Aids—Simulation General Terms Design, Experimentation, Verification Keywords overlay, double patterning lithography, interconnect var...

• Type: Conference
• Year: 2009
• Where: SLIP
• Authors: Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topaloglu
• Keywords: Computer Networks, Double Patterning Lithography, Interconnect, Patterning Lithography Techniques, SLIP 2009