3 search results - page 1 / 1 » Is overlay error more important than interconnect variations... |
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interco...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
NOCS
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...