Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory

Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly used by most memory synthesis tools, unnecessarily restricts the freedom of address generator synthesis. Therefore a memory model in which the address decoder is decoupled from the memory cell array is proposed. In order to demonstrate the benefits and limitations of this alternative memory model, synthesis results for a Shift Register based Address Generator that does not require address decoding are compared to those for a counter-based address generator that requires address decoding. Results show that delay can be nearly halved at the expense of increased area.

• Type: Conference
• Year: 2002
• Where: DATE
• Authors: Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke
• Keywords: Address Decoder, Address Generator, DATE 2002, Hardware, Memory Model