Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping

In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven multi-level clustering problem is NP-hard (in contrast to the fact that single-level performance-driven clustering can be solved in polynomial time optimally). Then, we present an efficient heuristic for two-level clustering for delay minimization. It can also provide area-delay trade-off by controlling the amount of node duplication. The algorithm is applied to Altera's latest APEX FPGA architecture which has a two-level hierarchy. Experimental results with combinational circuits show that with our performance-driven two-level clustering solution we can improve the circuit performance produced by the Quartus Design System from Altera by an average of 15% for APEX devices measured in terms of delay after final layout. To our knowledge this is the first in-depth study for the performance-driven multi-level...

• Type: Conference
• Year: 2001
• Where: DAC
• Authors: Jason Cong, Michail Romesis
• Keywords: DAC 2001, Design Automation, Performance-driven Multi-level Clustering, Performance-driven Two-level Clustering, Single-level Performance-driven Clustering