Petri net modeling of gate and interconnect delays for power estimation

In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit is converted into a HCHPN and simulated as a Petri net to get the switching activity estimate and thus the power values. The method is accurate and is significantly faster than other simulative methods. The HCHPN yields an average error of 4.9% with respect to Hspice for the ISCAS '85 benchmark circuits. The per-pattern simulation time is about 46 times lesser than PowerMill. Categories and Subject Descriptors B.7 [Hardware]: Integrated Circuits; B.7.2 [Integrated Circuits]: Design Aids--simulation General Terms Power Measurement

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Ashok K. Murugavel, N. Ranganathan
• Keywords: DAC 2002, Design Automation, Hardware Petri Net, Integrated Circuits, Switching Activity Estimate