Pipelined Memory Shared Buffer for VLSI Switches

ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perform better than multiple input queues or buffers, and the VLSI implementation of the former is not more expensive than the latter. We present a new organization for a shared buffer with its associated switching and cut-through functions. It is simpler and smaller than wide or interleaved organizations, and it is particularly suitable for VLSI technologies. It is based on multiple memory banks, addressed in a pipelined fashion. The first word of a packet is transferred to/from the first bank, followed by a ‘‘wave’’ of similar operations for the remaining words in the remaining banks. An FPGA-based prototype is operational, while standard-cell and full-custom chips are being submitted for fabrication. Simulation of the full-custom version indicates that, even in a conservative 1-micron CMOS technology...

• Type: Conference
• Year: 1995
• Where: SIGCOMM
• Authors: Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou
• Keywords: Communications, Multiple Input Queues, Multiple Memory Banks, SIGCOMM 1995, Switch Chips