Sciweavers

CODES
2010
IEEE
13 years 8 months ago
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
In high-level synthesis, pipelined designs are often restricted by the number of memory banks available to the synthesis system. Using multiple memory banks can improve the perfor...
Yosi Ben-Asher, Nadav Rotem
SAC
2008
ACM
13 years 10 months ago
A self-balancing striping scheme for NAND-flash storage systems
To use multiple memory banks in parallel is a nature approach to boost the performance of flash-memory storage systems. However, realistic data-access localities unevenly load eac...
Yu-Bin Chang, Li-Pin Chang
SIGCOMM
1995
ACM
14 years 2 months ago
Pipelined Memory Shared Buffer for VLSI Switches
ABSTRACT: Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perf...
Manolis Katevenis, Panagiota Vatsolaki, Aristides ...
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
14 years 2 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
CGO
2004
IEEE
14 years 2 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
FPL
2009
Springer
132views Hardware» more  FPL 2009»
14 years 2 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
CC
2007
Springer
126views System Software» more  CC 2007»
14 years 5 months ago
An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
K. Shyam, R. Govindarajan
ICASSP
2008
IEEE
14 years 5 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...
DAC
2004
ACM
14 years 12 months ago
Memory access scheduling and binding considering energy minimization in multi-bank memory systems
Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g....
Chun-Gi Lyuh, Taewhan Kim