Post-Layout Optimization for Deep Submicron Design

To reduce the number of synthesis and layout iterations, we present a new delay optimization technique, which inserts buers based on back-annotated detailed routing information. During optimization, inserted buers are assumed to be placed on the appropriate location of original wires so as to calculate accurate wire RC delay. With forwardannotated location information of inserted buers, the layout system attempts to preserve patterns of original wires using the ECO technique. Our experimental results show that this technique combined with the conventional gate

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emura, Naotaka Maeda
• Keywords: Computer Architecture, DAC 1996, Delay Optimization Technique, Inserted Buers, Original Wires