Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design

As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bus structures very data-dependent. Reducing the crosscoupling capacitance is crucial for achieving high-speed as well as lower power operation. In this paper, we propose two interconnect layout design methodologies for minimizing the cross-coupling e ect" in the design of full-custom datapath. Firstly, we describe the control signal ordering scheme which was shown to minimize the switching power consumption by 10 and wire delay by 15 for a given set of benchmark examples. Secondly, a track assignment algorithm based on evolutionary programming was used to minimize the crosscoupling capacitance. Experimental results have shown that the chip performance improvement as much as 40 can be obtained using the proposed interconnect schemes in various stages of the datapath layout optimization.

• Type: Conference
• Year: 1999
• Where: DAC
• Authors: Joon-Seo Yim, Chong-Min Kyung
• Keywords: Capacitance, Computer Architecture, DAC 1999, Inter-wire Coupling Capacitance, Load Capacitance